Overlay marks are important in fabrication of semiconductor, or integrated circuit (“IC”), devices because the devices are produced by aligning several layers of conductive, semiconductive, and insulative materials one atop the other. It is critical that each layer is precisely aligned with the previous layer so that the resultant circuits are functional and reliable. If the layers are not correctly aligned, some features may be short-circuited while others may be open circuited or have an unacceptably large resistance. Typically for each technology node, an overlay error threshold is specified in the x or y direction. In other words, each layer cannot shift more than a specified distance from another layer above or below. A shift greater than the specification causes an “alignment fail”, which increases cycle time because layers may have to be reworked.
During an overlay check, the position of the overlay mark on the wafer is typically sensed using a laser beam, which is bounced off the overlay mark to produce a reflected light signal reflected back to an inspector on a machine. The inspector then analyzes the reflected light signal to determine the exact position of the overlay mark. Notably, the quality of the signal reflected from the overlay mark is directly dependent on the the structure and the materials. Methods to improve overlay mark signals continue to be sought.